HT93LC46 1k 3-wire CMOS Serial EePROM Features. Operating voltage VCC Read: V~V Write: V~V Low power consumption Operating: 5mA max. HT93LC46 datasheet, HT93LC46 circuit, HT93LC46 data sheet: HOLTEK – CMOS 1K 3-Wire Serial EEPROM,alldatasheet, datasheet, Datasheet search site for. HT93LC46 datasheet, HT93LC46 circuit, HT93LC46 data sheet: HOLTEK – 1K 3- Wire CMOS Serial EEPROM,alldatasheet, datasheet, Datasheet search site for.
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The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. The following are the functional descriptions and timing diagrams of all seven instructions. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential.
After the write-all instruction set has been issued, the data writing is activated by the falling edge of CS. The information appearing in this Data Sheet is believed to be accurate at the time of publication. For the most up-to-date information, please visit our web site at http: No data can be written into the device in the programming disabled state.
The auto-timing write cycle includes an automatic erase-before-write capability. For successful instructions, CS must be low once after the instruction is sent. Stresses exceeding the range specified under?
These are stress ratings only.
ht93lc6 The DO pin will remain low but when the operation is over the DO pin will return to high and further instruction can be executed. However, Holtek assumes no responsibility arising from the use of the specifications described. There is an internal pull-up resistor on the ORG pin.
HT93LC46 Datasheet(PDF) – Holtek Semiconductor Inc
After power on, the device is by default in the EWDS state. The DO pin will remain low but when the operation is over, the DO pin will return to high and further instruction can be executed.
datwsheet After the erase-all instruction set has been issued, the data erase feature is activated by the falling edge of CS. Taipei Sales Office 4F-2, No. When the user selectable internal organization is arranged into 64? The 8 bits or 16 bits data stream is preceded by a logical? Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
After the data word has been read the internal address will be automatically incremented by 1 allowing the next consecutive data word to be read out without entering further address data.
HT93LC46 Datasheet PDF
By popular microcontroller, the versatile serial interface including chip select CSserial clock SKdata input DI and data output DO can be easily controlled. At both ht93lcc46 power on and power catasheet state the device automatically entered the disable mode.
Holtek reserves the right to dstasheet its products without prior notification. Since the internal auto-timing generator provides all timing signals for the write-all operation, so the SK clock is not required.
The DO pin will remain low but when the operation is over, the DO pin will return to high and further instructions can be executed. Since the internal auto-timing generator provides all timing signal for the erase-all operation, so the SK clock jt93lc46 not required. By so doing, the internal memory data can be protected. Test Conditions Input rise and fall time: Its bits of memory are organized into 64 words of 16 bits each when the ORG pin is connected to VCC or organized into words of 8 bits each when it is tied to VSS.
Since the internal auto-timing generator provides all timing signals for the internal erase, so datashete SK clock is not required. The HT93LC46 contains seven instructions: The data on DO pin changes during the low-to-high edge of SK signal. These serial instruction data presented at the DI input will be written into the device at the rising edge of SK.
Since the internal auto-timing generator provides all timing signal for the internal writing, so the SK clock is not required.